The rapid scaling of complementary metal-oxide semiconductor (CMOS) devices to ever smaller dimensions is currently leading the microelectronic industry to introduce major changes in the design of transistors.
Among them is the replacement of the SiO2 insulating layer with gate oxides having a higher dielectric constant and the introduction of metal electrodes, which introduce challenging issues. To meet the requirements of the next technological nodes, the silicon channel will soon have to be replaced by an alternative semiconductor.
Due to their high electron mobility, III-V compounds such as GaAs, InGaAs and InAs are ideal candidates to replace Si as the active material in the transistor channel.
However, an effective electrical passivation of the III-V materials remains an unsolved problem which prevents the development of functional MOS devices. In fact, the III-V/oxide interfaces are affected by a high density of defect states in the band gap which pin the Fermi level and are responsible for the poor electrical performances of the device. Various surface treatments such as surface passivation using sulfur compounds and surface cleaning using hydrogen or nitrogen plasma have been applied to reduce surface Fermi level pinning.
Patent application U.S. Pat. No. 6,159,834A discloses growing a GaGdOx oxide epitaxially on top of an III-V substrate. The GaGdOx oxide stabilizes the surface reconstruction of the III-V substrate, which minimizes the interface stress and leads to an unpinned Fermi level. However, the method limits the integration options to the use of the specific GaGdOx which can show significant leakage.
An alternative method described by De Souza et al. in Appl. Phys. Letters 92 153508 (2008) consists of depositing an amorphous layer of silicon on top of an III-V substrate (GaAs). However, this approach does not control the stress induced in the substrate and the electron-counting that governs the Fermi level pinning at the interface.
Therefore it is desirable to find a method that will effectively passivate an III-V substrate and will lead to a device with improved performance.